The Battle for Semiconductor Supremacy: Why Intel's High-NA Bet is critical for the US.

Understanding the technical details of Intel's approach might offer a reason to support their approach and back them in the race for Semiconductor Supremacy.

When news broke that Intel's chairman reportedly tried to sell fabs to TSMC, most observers focused on the business implications. But the real story lies in the fundamental technical incompatibility between two radically different approaches to cutting-edge semiconductor manufacturing, and why Intel's pursuit of a laudable goal is worth backing.

I’m not claiming to be a semiconductor manufacturing or advanced optical technology expert, but after more than 40 years in this industry, I’ve learned that we must pay close attention to its nuances and understand the history before forming opinions. The semiconductor physics at play is complex—and when it comes to lithography and its associated optics, the challenges are even greater.

Introduction

In the mid‑1980s, more than a dozen companies were at the forefront of semiconductor manufacturing, with industry leaders such as IBM, NEC, Toshiba, and Texas Instruments pushing the limits of chip technology. Today, that list has narrowed to just three “leading‑edge” manufacturers: TSMC, Samsung, and Intel. Remaining in this elite tier demands multi‑billion‑dollar investments, relentless R&D, and mastery of increasingly complex manufacturing techniques. Building a single state‑of‑the‑art fab for the next process node now costs $15–20 billion, plus billions more in node‑specific R&D (Deloitte, 2025; Semiconductor Industry Association [SIA], 2024). These staggering investments generate massive returns: in 2025, leading‑edge fabs collectively produced about $175 billion in revenue—roughly a quarter of the semiconductor industry’s ~$700 billion market. If the sector grows at a projected 6% compounded annual rate, fab revenues could rise to around $235 billion by 2030, representing a ~6.5% CAGR for fabrication alone (Mordor Intelligence, 2024; McKinsey & Company, 2025).

Central to this race of the Fabs to grow is lithography—the precision process of projecting intricate circuit patterns onto silicon wafers at nanometer scales. Lithography is the defining step in semiconductor fabrication, setting the ultimate limits on performance, power, and cost. Each new generation of lithography becomes a gateway that determines who leads and who falls behind.

The Great EUV Revolution: 32 Years in the Making

To understand today's strategic divide, we need to appreciate just how revolutionary our current technology is. EUV (Extreme Ultraviolet) lithography was first proposed by Hiroo Kinoshita in 1986 and didn't reach mass production until 2018—a staggering 32-year development cycle.

To elaborate a bit more, back in the 1970s and 1980s, fundamental research was conducted in labs and consortia (SRC, SEMI, SEMATECH) funded by deep government grants through agencies like DARPA. Most of that funding has dried up, leaving companies like Intel and TSMC to make these massive technological bets largely on their own.

These technologies take decades to engineer and master. The transition from i-line lithography (365nm) in the 1980s to KrF DUV (248nm) in the 1990s to ArF immersion (193nm) in the 2000s to today's EUV (13.5nm) represents continuous evolution over 40+ years of development.

Before EUV, the semiconductor world was dominated by immersion lithography, primarily using Ultra Violet light. The wavelength of light used started from about 365 nm. Japanese companies like Nikon and Canon were the undisputed leaders. Wavelength progressively went from 365nm down to 193 nm as shown in the graph below.

But when EUV (or Extreme Ultra Violet light) technology proved viable, where the wavelength dropped from 193 nm down to 13.5 nm (!!), both the Japanese companies failed to make the transition to mass manufacturing and essentially exited the advanced lithography space, leaving ASML as the sole monopoly supplier of EUV systems in 2018. It is important to realize that Cymer a San Diego based company was a key acquisition by ASML back in 2013 that unlocked its ability to get the light source perfected for EUV.

Fig 1: The evolution of Lithography while understanding the Industry Players

This transformation was far more than a mere business shift—it was a profound technological revolution. Decades of fundamental research and innovation by the global semiconductor community have been meticulously deployed to achieve the advanced technology nodes we implement today.

The Current State: Low-NA EUV Dominance

Figure 2: Raleigh's Criterion

Lithography resolution is fundamentally defined by the Rayleigh criterion (Figure 2), which relates the smallest printable feature (CD) to the wavelength (λ) of the light source and the optical system’s numerical aperture (NA), scaled by a process constant K1.

Using ASML's technical leap in EUV, Samsung pioneered commercial EUV production in 2018, followed by TSMC in 2019. Both companies adopted what's called "Low-NA" (Numerical Aperture value of 0.33) EUV systems using 13.5nm wavelength light sources.

For the past 6-7 years, Low-NA EUV has been the state of the art, capable of printing line geometries at about 34nm pitch. This technology has been one of the legs that has powered the current surge in semiconductors and enabled the AI boom we're experiencing today.

Intel's Radical Gamble: The High-NA Leap

But Intel chose a dramatically different path. Instead of following the established Low-NA approach, Intel received the world's first High-NA EUV system in 2024, betting on 0.55 Numerical Aperture technology that can theoretically print features down to 8nm pitch.

This isn't just an incremental improvement—it's a fundamental philosophical difference in manufacturing strategy. While TSMC extended Low-NA's lifespan through techniques like double patterning (exposing the same layer multiple times with different patterns), Intel decided to leapfrog directly to the next generation.

The trade-offs are significant:

• High-NA advantages: Fewer processing steps per layer, lower operational costs, smaller geometries, and potentially leapfrogging the competition for the next 10 years.

• High-NA challenges: Systems cost ~$300M vs ~$200M for Low-NA, reduced field sizes, higher complexity

High-NA EUV, while built on existing EUV foundations, still requires years of development and represents another major leap forward. The good news is that ASML, the EUV behemoth, recognizes this and is fully engaged in developing high-NA solutions and is pouring billions into this research as well. Intel has the opportunity to leverage this and come out of the gates faster than its competition, but it will need the backing of all interested parties that want the US to succeed.

Why TSMC and Intel Can't Just Merge Technologies

At least as of today, TSMC and Intel's Fab approaches are like Oil and water. They don't mix well.

Different Process Philosophies: TSMC has spent years optimizing its manufacturing around Low-NA EUV with sophisticated multiple patterning techniques. Intel has committed to High-NA EUV for its advanced nodes. These aren't just different tools—they're completely different approaches to solving the same fundamental physics problems.

Incompatible Expertise: TSMC's workforce lacks experience with Intel's EUV-based process flows, making it nearly impossible to help Intel improve its Intel 3 or Intel 18A fabrication technologies without essentially starting from scratch.

The Strategic Choice: Wait or Lead?

High-NA is likely the future, whether we like it or not. TSMC has indicated it will probably move to High-NA by 2030, but Intel is attempting to achieve a 3-5 year head start if it can make it work today.

This represents a classic strategic dilemma: Do we wait for the market leader (TSMC) to mature the technology, or do we bet on ourselves to invest in and leapfrog the current state of the art?

The Forgotten Player: Zeiss

In the meantime, keep an eye on Zeiss, the German optics company that isn't just "likely to be" the leader—they are the exclusive supplier of the specialized mirrors required for High-NA systems. ASML and Carl Zeiss SMT have been in close partnership for more than 30 years, and around 1,500 of the more than 7,500 employees at ZEISS SMT are currently working on the development and realization of High-NA-EUV lithography.

The technical necessity is clear: since most materials absorb EUV light, traditional lenses would absorb the light in the system. Instead, Zeiss developed a brand-new optical system that uses ultrasmooth, multilayer mirrors. Zeiss manufactures these critical mirrors because conventional glass lenses simply cannot work with 13.5nm EUV light.

ASML has made billion-euro investments in Zeiss' SMT division to help the development of high-numerical-aperture optics, underlining just how essential this partnership is. Together with its strategic partners ASML and TRUMPF, ZEISS is the global market leader in EUV technology – thanks to around 25 years of research and development.

In the EUV ecosystem, while ASML gets the headlines as the system integrator, Zeiss provides the critical optical components that make both current Low-NA and future High-NA systems physically possible. Without Zeiss's ultra-precise multilayer mirrors, the entire EUV revolution would be impossible.

Conclusion: More Than Just Business

Intel's High-NA bet represents one of the boldest technological gambles in recent semiconductor history. If successful, it could provide a significant competitive advantage. If it fails, it could set Intel back years while competitors perfect their Low-NA approaches.

Understanding these technical nuances is crucial for anyone trying to make sense of today's semiconductor landscape. The physics is hard, the engineering is harder, and the stakes couldn't be higher for the future of computing technology.

The semiconductor industry continues to push the boundaries of what's physically possible. Whether Intel's High-NA gamble pays off will determine not just the company's future, but potentially the entire trajectory of advanced semiconductor manufacturing in the coming decade.